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| MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP M66220SP/FP M66220SP/FP 256256 x 8-BIT MAIL-BOX x 8-BIT MAIL-BOX DESCRIPTION The M66220 is a mail box that incorporates a complete CMOS shared memory cell of 256 x 8-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports. PIN CONFIGURATION (Top view) CHIP SELECT CSA 1 INPUT WRITE ENABLE WEA 2 INPUT NOT READY Not Ready A 3 OUTPUT OUTPUT ENABLE OEA INPUT A0A A1A A2A A PORT A3A ADDRESS INPUT A4A A5A A6A A7A I/O0A I/O1A I/O2A A PORT I/O3A DATA I/O I/O4A I/O5A I/O6A I/O7A GND 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 VCC CHIP SELECT 41 CSB INPUT WRITE ENABLE 40 WEB INPUT 39 Not Ready B NOT READY OUTPUT 38 OEB OUTPUT ENABLE INPUT 37 A0B 36 A1B 35 A2B 34 A3B B PORT ADDRESS 33 A4B INPUT 32 A5B 31 A6B 30 A7B 29 I/O7B 28 I/O6B 27 I/O5B 26 I/O4B B PORT DATA I/O 25 I/O3B 24 I/O2B 23 I/O1B 22 I/O0B FEATURES * * * * * * * * * * Memory configuration of 256 x 8 bits High-speed access, address access time 40ns (typ.) Complete asynchronous accessibility from ports A and B Completely static operation Built-in port arbitration function Low power dissipation CMOS design 5V single power supply Not Ready output pin is provided (open drain output) TTL direct-coupled I/O 3-state output for I/O pins M66220SP/FP APPLICATION Inter-MPU data transfer memory, buffer memory for image processing system. Outline 42P4B 42P2R-A BLOCK DIAGRAM NOT READY OUTPUT Not Ready A 3 WRITE WEA 2 ENABLE INPUT CHIP CSA 1 SELECT INPUT OUTPUT OEA 4 ENABLE INPUT I/O0A 13 I/O1A 14 I/O2A 15 I/O3A 16 A PORT DATA I/O I/O4A 17 I/O5A 18 I/O6A 19 I/O7A 20 A0A A1A A2A A3A A4A A5A A6A A7A 5 6 7 8 9 10 11 12 VCC 42 NOT READY 39 Not Ready B OUTPUT WRITE ENABLE INPUT CHIP 41 CSB SELECT INPUT OUTPUT 38 OEB ENABLE INPUT 22 I/O0B 23 I/O1B 24 I/O2B 25 I/O3B B PORT DATA I/O 26 I/O4B 27 I/O5B 28 I/O6B 29 I/O7B 40 WEB 37 36 35 34 33 32 31 30 A0B A1B A2B A3B A4B A5B A6B A7B CONTROL CIRCUIT ARBITRATION CIRCUIT CONTROL CIRCUIT ~ A7A 8 I/O BUFFER A7B I/O BUFFER 8 A PORT ADDRESS INPUT 8 ROW/COLUMN DECODER MEMORY ARRAY OF 256-WORD x 8-BIT CONFIGURATION ~ OEA WEA A0A A0B WEB OEB ROW/COLUMN DECODER 8 B PORT ADDRESS INPUT 21 GND 1 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX FUNCTION The M66220 is a mail box most suitable for inter-MPU data transfer which is used in a multiport mode. Provision of two pairs of addresses and data buses in its shared memory cell of 256 x 8 bit configuration allows independent and asynchronous read/write operations from/to two access ports of A and B individually. This allows access to shared memory as simple RAM when viewing from one MPU. The concurrent accessibility to shared memory from two MPUs provides remarkable improvement of a multiport mode processor system in throughput. The arbitration function incorporated in the chip decides the first-in port to assign a higher priority to the access from one MPU, even if two MPUs contend for selection of the same address in shared memory from ports A and B. A Not Ready signal "L" is output to the last-in port and invalidates any access from the other MPU. As a write operation to memory, one of addresses A0 to A7 is specified. Table 1 Mode Settings of Ports (A0A ~ A7A A0B ~ A7B) A port input CSA H x L L x x WEA x x L H x x OEA x x x L x x CSB x H x x L L B port input WEB x x x x L H OEB x x x x x L Flag Not Ready A H H H H H H The CS signal is set to "L" to place one of I/O pins in the input mode. Also, the WE signal is set to "L". Data at the I/O pin is thus written into memory. As a read operation, the WE signal is set to "H". Both CS signal and OE signal are set to "L" to place one of I/O pins in the output mode. One of addresses A0 to A7 is specified. Data at the specified address is output to the I/O pin. When the CS signal is set to "H", the chip enters a non-select state which inhibits a read and write operation. At this time, the output is placed in the floating state (high impedance state), thus allowing OR tie with another chip. When the OE signal is set to "H", the output enters the floating state. In the I/O bus mode, setting the OE signal to "H" at a write time avoids contention of I/O bus data. When the CS signal is set to Vcc, the output enters the full stand-by state to minimize supply current (See Tables 1 and 2). Not Ready B H H H H H H Operation A port is set to the non-select mode. B port is set to the non-select mode. A port is set to the write mode for memory. A port is set to the read mode for memory. B port is set to the write mode for memory. B port is set to the read mode for memory. Table 2 Basic Functions of Ports CS H L L L WE x L H H OE x x L H Mode Non-select Write Read I/O pin High impedance DIN DOUT High impedance ICC Stand-by Operation Operation Operation Note 1: x indicates "L" or "H". (Irrelevant) "H" = High level, "L" = Low level 2 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX FUNCTIONAL DESCRIPTION Arbitration Function The M66220 has asynchronous accessibility from two independent ports to shared memory, thus remarkably improving the throughput of the entire processor system used in the multiport mode. On the other hand, this accessibility causes a problem of contending for selecting the same address in shared memory during the addressing from both ports. If the same address is contentionally selected, the following four basic operations are possible depending on an access mode set from both ports: (1) A port .......... Read B port .......... Read (2) A port .......... Read B port .......... Write (3) A port .......... Write B port .......... Read (4) A port .......... Write B port .......... Write In this case, when both ports are operating in the read mode as given in (1), correct data is read to both ports and the contents of memory are not destroyed. There is no special problem. If the other port is in the read mode while one port is operating in the write mode as given in (2) or (3), however, data is written correctly but the data read from the other port in the read mode may change during the same cycle. This comes into question. When both ports are operating in the write mode as given in(4), reverse data is written into each port and the contents of memory may become uncertain. Consequently, no result will be guaranteed. The M66220 incorporated an arbitration function circuit to solve such problems when contentionally selecting an address from both ports. The arbitration function decides which of A and B ports determines an address first, and unconditionally assigns access priority to the first-in port (At this time, the Not Ready signal holds "H"). As for the last-in port operation, the function inhibits any write to that port from MPU at the same time when "L" is output to the Not Ready output pin at the port regardless of a read or write operation during the period of address matching of both ports. If the address of the first-in port changes after that and both ports do not have the same address, the Not Ready output is reset to "H" and the access in the stopped state is accepted from the last-in port. If the same address is selected by an address input from both ports simultaneously, a decision by the arbitration function on the chip also affords access only from one port, and outputs "L" to the Not Ready output for the other port invalidate any access from MPU. Tables 3 and 4 give the relationship between the port arbitration function and port access. 3 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX Arbitration Function and Port Access Contention No.1 (Address control) Table 3 gives the port access states and the Not Ready signal output states if the same address is selected in shared memory by an address Table 3 Contention Processing by Address Input Address setting when selecting same address First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port Simultaneous A and B ports Mode setting Read Read Read Read Write Write Write Write A port Access , , , , , x , x Arbitration Resolved Not Ready A H L H L H L H L Mode setting Read Read Write Write Read Read Write Write B port Access , , x , , , x , Arbitration Resolved input set from A and B ports with CSA = CSB = "L". CSA = CSB = "L" Not Ready B L H L H L H L H Contention No.2 (CS control) Table 4 gives the port access states and the Not Ready signal output states when setting the CS inputs from A and B ports valid, and Table 4 Contention Processing by CS Input CS input set when selecting same address First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port First-in A port First-in B port Simultaneous A and B ports Note 2: "H" = High level, "L" = Low level selecting the same address in shared memory with A0A to A7A=A0B to A7B. A0A ~ A7A = A0B ~ A7B Mode setting Read Read Read Read Write Write Write Write A port Access , , , , , x , x Arbitration Resolved Not Ready A H L H L H L H L Mode setting Read Read Write Write Read Read Write Write B port Access , , x , , , x , Arbitration Resolved Not Ready B L H L H L H L H 4 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70C, unless otherwise noted) Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature range Conditions When defining GND pin as a reference. Ta = 25C Ratings -0.3 ~ +7.0 -0.3 ~ VCC + 0.3 0 ~ VCC 700 -65 ~ 150 Unit V V V mW C RECOMMENDED OPERATING CONDITIONS Symbol VCC GND VI Topr Parameter Supply voltage Ground Input voltage Operating temperature range Min. 4.5 0 0 Limits Typ. 5.0 0 Max. 5.5 VCC 70 Unit V V V C ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, Vcc=5V10%, unless otherwise noted) Symbol VIH VIL VOH VOL VOL IIH IIL IOZH IOZL Parameter "H" input voltage "L" input voltage "H" output voltage (I/O) "L" output voltage (I/O) Open drain "L" output voltage (Not Ready) "H" input current "L" input current Off state "H" output current Off state "L" output current Test conditions Min. 2.2 -0.3 2.4 Limits Typ. Max. VCC+0.3 0.8 0.5 0.5 10.0 -10.0 10.0 -10.0 Unit V V V V V A A A A IOH = -2mA IOL = 4mA IOL = 8mA VI = VCC VI = GND CS = VIH or OE = VIH VO = VCC CS = VIH or OE = VIH VO = GND CS < 0.2V, Another input VIN > VCC - 0.2V or VIN < 0.2V, Output pin open CSA, CSB = VIH CSA or CSB = VIH IOUT = 0mA (Active port output pin open) CSA, CSB > VCC - 0.2V Another input VIN > VCC - 0.2V or VIN < 0.2V CSA or CSB > VCC - 0.2V Another input VIN > VCC - 0.2V or VIN < 0.2V, IOUT = 0mA (Active port output pin open) ICC ISB1 ISB2 Static current dissipation (active) Two-port stand-by One-port stand-by Stand-by current 60 5 60 mA mA mA ISB3 Two-port full stand-by 0.1 mA ISB4 One-port full stand-by 30 mA CI CO Input capacitance Output capacitance in off state 10 15 pF pF Notes 3: The direction in which current flows into the IC is defined as positive (no sign). 4: The above typical values are standard values for VCC = 5V and Ta = 25C. 5 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX SWITCHING CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V10%, unless otherwise noted) Read cycle Symbol tCR ta(A) ta(CS) ta(OE) tdis(CS) tdis(OE) ten(CS) ten(OE) tv(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after CS (Note 5) Output disable time after OE (Note 5) Output enable time after CS (Note 5) Output enable time after OE (Note 5) Data effective time after Address Min. 70 Limits Typ. Max. 70 70 35 35 35 5 5 10 Unit ns ns ns ns ns ns ns ns ns TIMING REQUIREMENTS (Ta = 0 ~ 70C, VCC = 5V10%, unless otherwise noted) Write cycle Symbol tCW tw(WE) tsu(A) tsu(A-WEH) tsu(CS) tsu(D) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) Parameter Write cycle time Write pulse width Address setup time Address setup time for rise of WE. Chip select setup time (for WE) Data setup time Data hold time Write recovery time Output disable time after WE (Note 5) Output disable time after OE (Note 5) Output enable time after WE (Note 5) Min. 70 45 0 65 65 40 0 0 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns 35 35 0 Note 5: The time required for the output to change from a steady state to 500mV under the load conditions shown in Fig 2. This parameter is guaranteed but is not tested at shipment. NOT READY TIMING (Ta = 0 ~ 70C, VCC = 5V10%, unless otherwise noted) Symbol tNAA tNDA tNAC tNDC tAPS tNO tNW Parameter Not Ready access time from Address Not Ready disable time from Address Not Ready access time from CS Not Ready disable time from CS Arbitration priority setup time Data output access time from Not Ready. Write hold time from Not Ready. Min. Limits Typ. Max. 50 50 50 50 0 65 Unit ns ns ns ns ns ns ns 15 6 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX TIMING DIAGRAM Read Cycle (WE = VIH) Read cycle No.1 (Address control) (CS = OE = VIL) tCR A0~A7 ta(A) tv(A) I/O0~I/O7 (DOUT) Previous cycle data Data output determined tv(A) Read cycle No.2 (CS control) tCR A0~A7 ta(A) CS ta(CS) ten(CS) OE ta(OE) ten(OE) I/O0~I/O7 (DOUT) Data output determined High impedance tdis(OE) tdis(CS) 7 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX Write Cycle Write cycle No.1 (WE control) See Notes 6, 7 and 8. tCW A0~A7 tsu(A-WEH) tsu(CS) CS tsu(A) WE tsu(D) I/O0~I/O7 (DIN) th(D) tw(WE) trec(WE) Data input determined OE tdis(OE) I/O0~I/O7 (DOUT) Write cycle No.2 (CS control) See Notes 6, 7 and 8. tCW A0~A7 tsu(A-WEH) tsu(A) CS tsu(CS) trec(WE) tw(WE) WE tsu(D) I/O0~I/O7 (DIN) ten(CS) I/O0~I/O7 (DOUT) Notes 6: 7: 8: 9: The WE of the port must be set to "H" when an address input changes. A write operation is performed during the overlap period when both CS and WE are "L". Do not apply any negative-phase signal from outside when an I/O pin is in output state. The shaded part means a state in which a signal can be "H" or "L". th(D) Data input determined tdis(WE) 8 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX Contention Read Cycle (WE = VIH, OE = VIL) Contention read cycle No.1 (Address control) See Notes 10 and 11. Address A (Address B) tAPS Address B (Address A) Address matching Address not matching tNAA tNDA Not Ready B (Not Ready A) tv(A) tNO I/O0B~I/O7B (I/O0A~I/O7A) Previous cycle data ta(A) Address A = Address B Data output determined Contention read cycle No.2 (CS control) See Notes 10 and 12. Addresses A&B Address matching CSA (CSB) tAPS CSB (CSA) tNAC Not Ready B (Not Ready A) ten(CS) I/O0B~I/O7B (I/O0A~I/O7A) ta(CS) Address A = Address B Notes 10: The Not Ready output of the first-in port holds "H". 11: When CS is set to "L" before the address input is determined. 12: When the address input is determined before CS transition to "L". tNDC tNO Data output determined 9 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX Contention Write Cycle Contention write cycle No.1 (WE control) See Notes 6, 8, 10 and 11. Address A (Address B) tAPS Address B (Address A) tNAA Not Ready B (Not Ready A) tsu(A-WEH) tw(WE) tNW tNDA Address matching tsu(A) WEB (WEA) tsu(D) I/O0B~I/O7B (I/O0A~I/O7A) (DIN) tdis(WE) I/O0B~I/O7B (I/O0A~I/O7A) (DOUT) th(D) Data input determined ten(WE) Address A = Address B Contention write cycle No.2 (CS control) See Notes 6, 8, 10 and 12. Addresses A&B Address matching CSA (CSB) tAPS CSB (CSA) tNAC Not Ready B (Not Ready A) tsu(CS) tw(WE) WEB (WEA) tsu(D) I/O0B~I/O7B (I/O0A~I/O7A) (DIN) th(D) tNW tNDC Data input determined ten(CS) tdis(WE) ten(WE) I/O0B~I/O7B (I/O0A~I/O7A) (DOUT) Address A = Address B 10 MITSUBISHI DIGITAL ASSP M66220SP/FP 256 x 8-BIT MAIL-BOX SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT Input pulse level Input pulse rise/fall time Input timing reference voltage Output timing decision voltage Output load : VIH = 3.0V, VIL = 0V : tr/tf = 5ns : 1.5V : 1.5V : Figure 1 ~ 3 (The capacitance includes stray wiring capacitance and the probe input capacitance.) + 5V + 5V + 5V 1250 I/O I/O 1250 Not Ready 575 775 100pF 775 5pF 50pF Fig 1. I/O Output Load Fig 2. I/O Output Load (to ten, tdis) Fig 3. Not Ready Output Load 11 |
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